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PCI Interrupt Generation
PCI Interrupt Generation
To initiate an interrupt, the backend asserts the EXT_INTN input ( Figure 6-32 ). Two cycles later, the PCI INTAN
interrupt signal is asserted.
cycle
I0
I1
I2 R0 R1 R2 R3 R4 R5 R6
W0 W1 W2 W3 W4 W5 W6 W7
clk
idsel
framen
cben[3:0]
ad[31:0]
A
ADDR
0
Int Register
B
ADDR
0
Int Register
par
devseln
irdyn
trdyn
dp_start
dp_done
rd_cyc
wr_cyc
ext_intn
intan
Figure 6-32 · PCI Interrupt Generation and Acknowledge Sequence
When INTAN is asserted, the Master can read the Interrupt Status register to verify which device is driving INTAN
(cycles R0–R6). Once it has determined which device and the reason for the interrupt, it writes to the requesting
Interrupt Control/Status register to clear the interrupt request (cycles W0–W6).
The Interrupt Control/Status register can be accessed through the configuration space or through a memory BAR if the
DMA registers are mapped to memory space.
v4.0
81
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